LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE WORK.ic_1;

--TESTBENCH DO IC_1(AND)

ENTITY tb_ic_1_and IS
END tb_ic_1_and;

ARCHITECTURE logic OF tb_ic_1_and IS

COMPONENT ic_1
    PORT(pin1, pin2, pin4, pin5, pin9, pin10, pin12, pin13: IN STD_LOGIC; 
        pin3, pin6, pin8, pin11: OUT STD_LOGIC);
END COMPONENT;

SIGNAL in_1, in_2, s_pin3, s_pin6, s_pin8, s_pin11: STD_LOGIC;

FOR and_test: ic_1 USE ENTITY WORK.ic_1(and_ic);

BEGIN
    and_test: ic_1
    PORT MAP(pin1=>in_1, pin2=>in_2, pin3=>s_pin3,
		  pin4=>in_1, pin5=>in_2, pin6=>s_pin6,
		  pin8=>s_pin8, pin9=>in_1, pin10=>in_2,
		  pin11=>s_pin11, pin12=>in_1, pin13=>in_2); 
    PROCESS
        TYPE pattern_record IS RECORD
            vi_pin1, vi_pin2, vo_pin3, vo_pin6, vo_pin8, vo_pin11: STD_LOGIC;
        END RECORD;
        TYPE pattern_tests IS ARRAY (NATURAL RANGE <>) OF pattern_record;
            CONSTANT patterns : pattern_tests :=
            (
                ('0', '0', '0', '0', '0', '0'),
                ('1', '0', '0', '0', '0', '0'),
                ('0', '1', '0', '0', '0', '0'),
                ('1', '1', '1', '1', '1', '1')
            );
    BEGIN
        FOR i IN patterns'RANGE LOOP
				in_1 <= patterns(i).vi_pin1;
				in_2 <= patterns(i).vi_pin2;

            WAIT FOR 100 ps;
				ASSERT s_pin3 = patterns(i).vo_pin3 REPORT "VALOR DO PINO 3 ERRADO" SEVERITY error;
				ASSERT s_pin6 = patterns(i).vo_pin6 REPORT "VALOR DO PINO 6 ERRADO" SEVERITY error;
				ASSERT s_pin8 = patterns(i).vo_pin8 REPORT "VALOR DO PINO 8 ERRADO" SEVERITY error;
				ASSERT s_pin11 = patterns(i).vo_pin11 REPORT "VALOR DO PINO 11 ERRADO" SEVERITY error;
        END LOOP;
        ASSERT false REPORT "END." SEVERITY note;
        WAIT;
    END PROCESS;
END logic;
